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參數(shù)資料
| 型號(hào)： | P89V52X2FBD,157 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 9/57頁(yè) |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 44-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LQFP |
| 包裝： | 托盤(pán) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱(chēng)： | 568-4250 935282529157 P89V52X2FBD |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
17 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.8.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a xed divide-by-32 prescaler. Figure 10 shows Mode 0 operation.
In this mode, the Timer register is congured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt ag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON (Figure 8). The GATE bit is in the TMOD
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run ag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 10). There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
6.8.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See Figure 11.
3
IE1
Interrupt 1 Edge ag. Set by hardware when external interrupt 1
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 1.
1
IE0
Interrupt 0 Edge ag. Set by hardware when external interrupt 0
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 0.
Table 14.
TCON - Timer/Counter control register (address 88H) bit description …continued
Bit
Symbol
Description
Fig 10. Timer/Counter 0 or 1 in Mode 0 (13-bit counter)
002aaa519
osc/6
Tn pin
TRn
TnGate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
overflow
interrupt
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89V52X2FN | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM |
| P89V52X2FN,112 | 功能描述:8位微控制器 -MCU 80C51 8K FL / 256 RM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89V660 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_08 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_0811 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
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