參數(shù)資料
型號(hào): P89LPC954FBD44,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 28/69頁(yè)
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
標(biāo)準(zhǔn)包裝: 160
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
34 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.17.6 Timer overow toggle output
Timers 0 and 1 can be congured to automatically toggle a port output whenever a timer
overow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the rst
timer overow when this mode is turned on.
7.18 RTC/system timer
The P89LPC952/954 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again
and the RTCF ag will be set. The clock source for this counter can be either the CPU
clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as
the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use
CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs
to the default state.
7.19 UARTs
The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional
80C51 UART except that Timer 2 overow cannot be used as a baud rate source. The
P89LPC952/954 does include an independent Baud Rate Generator for each UART
(BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the
oscillator (divided by a constant), Timer 1 overow, or the independent Baud Rate
Generator associated with the specic UART. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt options.
The UARTs can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU
clock/32 or CPU clock/16.
7.19.1 Mode 0
Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are
transmitted or received, LSB rst. The baud rate is xed at 1
16 of the CPU clock
frequency.
7.19.2 Mode 1
10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0),
8 data bits (LSB rst), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8_n in Special Function Register SnCON. The baud rate is variable and is
determined by the Timer 1 overow rate or the Baud Rate Generator (described in Section
7.19.3 Mode 2
11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0),
8 data bits (LSB rst), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8_n in SnCON) can be assigned the value of ‘0’ or ‘1’. Or,
for example, the parity bit (P, in the PSW) could be moved into TB8_n. When data is
received, the 9th data bit goes into RB8_n in Special Function Register SnCON, while the
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