參數(shù)資料
型號(hào): P89LPC954FBD44,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 13/69頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
標(biāo)準(zhǔn)包裝: 160
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
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P89LPC952_954_4
NXP
B
.V
.2008.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.04
24
J
u
ly
2008
20
of
69
NXP
Semiconductor
s
P89LPC952/954
8-bit
micr
ocontr
oller
with
10-bit
ADC
[1]
Indicates SFRs that are bit addressable.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable.
[4]
The RSTSRC register reects the cause of the P89LPC952/954 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[5]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[6]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7]
The only reset source that affects these SFRs is power-on reset.
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON[1]
Timer 0 and 1
control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
0000 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TMOD
Timer 0 and 1
mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
0000 0000
TRIM
Internal
oscillator trim
register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog
control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog
feed 1
C2H
WFEED2
Watchdog
feed 2
C3H
Table 4.
Special function registers …continued
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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