參數(shù)資料
型號(hào): P89LPC932A1FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 36/64頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP
622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-1286-5
935276132529
P89LPC932A1FDH-S
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
41 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.27 Data EEPROM
The P89LPC932A1 has 512 B of on-chip data EEPROM. The data EEPROM is SFR
based, byte readable, byte writable, and erasable (via row ll and sector ll). The user can
read, write and ll the memory via SFRs and one interrupt. This data EEPROM provides
400000 minimum erase/program cycles for each byte.
Byte mode: In this mode, data can be read and written one byte at a time.
Row ll: In this mode, the addressed row (64 bytes) is lled with a single value. The
entire row can be erased by writing 00H.
Sector ll: In this mode, all 512 bytes are lled with a single value. The entire sector
can be erased by writing 00H.
After the operation nishes, the hardware will set the EEIF bit, which if enabled will
generate an interrupt. The ag is cleared by software.
7.28 Flash program memory
7.28.1 General description
The P89LPC932A1 ash memory provides in-circuit electrical erasure and programming.
The ash can be erased, read, and written as bytes. The Sector and Page Erase functions
can erase any ash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase
the entire program memory. ICP using standard commercial programmers is available. In
addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.
On-chip erase and write timing generation contribute to a user-friendly programming
interface. The P89LPC932A1 ash reliably stores memory contents even after
400000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC932A1 uses VDD as the supply voltage to
perform the Program/Erase algorithms.
7.28.2 Features
Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP.
Internal xed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
Boot vector allows user-provided ash loader code to reside anywhere in the ash
memory space, providing exibility to the user.
Any ash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the ash for each sector.
400000 typical erase/program cycles for each byte.
20 year minimum data retention.
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