參數(shù)資料
型號: P89CV51RC2FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 37/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-TQFP
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
其它名稱: 568-4255
935284104557
P89CV51RC2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
42 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Fig 16. SPI master-slave interconnection
002aaa528
8-BIT SHIFT REGISTER
MSB master LSB
SPI
CLOCK GENERATOR
MISO
MOSI
SCK
SS
8-BIT SHIFT REGISTER
MSB slave LSB
VSS
VDD
Table 27.
SPCR - SPI control register (address D5H) bit allocation
Reset source(s): any reset; reset value: 0000 0000B.
Bit
7
6
5
4
3
2
1
0
Symbol
SPIE
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Table 28.
SPCR - SPI control register (address D5H) bit description
Bit
Symbol
Description
7
SPIE
SPI interrupt enable. If both SPIE = 1 and ES = 1, SPI interrupts are enabled.
6
SPEN
SPI enable bit. When set enables SPI.
5
DORD
Data transmission order. 0 = MSB rst; 1 = LSB rst in data transmission.
4
MSTR
Master/Slave select. 1 = Master mode, 0 = Slave mode.
3
CPOL
Clock polarity. 1 = SPICLK is HIGH when idle (active LOW), 0 = SPICLK is
LOW when idle (active HIGH).
2
CPHA
Clock Phase control bit. 1 = shift-triggered on the trailing edge of the clock;
0 = shift-triggered on the leading edge of the clock.
1
SPR1
SPI clock Rate select bit 1. Along with SPR0 controls the SPICLK rate of the
device when a master. SPR1 and SPR0 have no effect on the slave; see
0
SPR0
SPI clock Rate select bit 0. Along with SPR1 controls the SPICLK rate of the
device when a master. SPR1 and SPR0 have no effect on the slave; see
Table 29.
SPCR - SPI control register (address D5H) clock rate selection
SPR1
SPR0
SPICLK = fosc divided by
6-clock mode
12-clock mode
00
2
4
01
8
16
1
0
32
64
1
64
128
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