參數(shù)資料
型號(hào): P89CV51RC2FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 19/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-TQFP
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
其它名稱: 568-4255
935284104557
P89CV51RC2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
26 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.4 Timers/counters 0 and 1
The two 16-bit timer/counter registers: Timer 0 and Timer 1 can be congured to operate
either as timers or event counters (see Table 13 and Table 14).
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can
think of it as counting machine cycles. Since a machine cycle consists of six oscillator
periods, the count rate is 1
6 of the oscillator frequency.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles
(12 oscillator periods) for a 1-to-0 transition to be recognized, the maximum count rate is
1
12 of the oscillator frequency. There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at least once before it changes, it
should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’
selection, Timer 0 and Timer 1 have four selectable operating modes.
Program status bit, boot vector,
6
×/12× bit
Input parameters:
R1 = 06H or 86H (WDT feed)
DPL = 00H = program status bit
DPL = 01H = program boot vector
DPL = 02H = 6
×/12× bit
ACC = boot vector value to program
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Read security bits, status bit, boot
vector
Input parameters:
ACC = 07H or 87H (WDT feed)
DPL = 00H = security bits
DPL = 01H = status bit
DPL = 02H = boot vector
Return parameter(s):
ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK
Erase page
Input parameters:
R1 = 08H or 88H (WDT feed)
DPH = page address high byte
DPL = page address low byte
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Table 12.
IAP function calls …continued
IAP function
IAP call parameters
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