參數(shù)資料
型號： P87CL54X2BDH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family
中文描述： 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PDSO38
封裝： 4.40 MM, 0.50 MM PITCH, PLASTIC, SHRINK, SOT-510-1, TSSOP-38
文件頁數(shù)： 33/47頁
文件大小： 301K
代理商： P87CL54X2BDH
Philips Semiconductors
Product data
P87CL52X2/54X2
80C51 8-bit microcontroller family
8K/16K OTP 256 bytes RAM ROMless low voltage
(1.8 V to 3.3 V), low power, high speed (33 MHz)
2003 May 14
33
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, V
CC
= 1.8 V to 3.3 V, V
SS
= 0 V (12 MHz devices)
SYMBOL
PARAMETER
TEST
LIMITS
TYP
1
UNIT
CONDITIONS
MIN
MAX
V
IL
V
IH
V
IH1
V
OL
V
OL1
V
OH
Input low voltage
–0.5
0.2 V
CC
– 0.05
V
CC
+0.5
V
CC
+0.5
0.3
V
Input high voltage (ports 0, 1, 2, 3, EA)
0.35 V
CC
+ 0.55
0.7 V
CC
–
V
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3
6
Output low voltage, port 0, ALE, PSEN
6, 5
Output high voltage, ports 1, 2, 3
3
V
I
OL
= 1.6 mA
I
OL
= 3.2 mA
I
OH
= –30
μ
A
V
CC
= 1.8 V
I
OH
= –3.2 mA
V
IN
= 0.4 V
V
IN
= 1.25 V
V
DD
= 3.3 V
0.45 V < V
IN
<
V
CC
– 0.3 V
See note 4
V
–
0.4
V
V
CC
– 0.6
–
V
V
OH1
Output high voltage (port 0 in external bus
mode), ALE
7
, PSEN
3
V
CC
– 0.7
–
V
I
IL
Logical 0 input current, ports 1, 2, 3
–
–40
μ
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
–
–300
μ
A
I
LI
Input leakage current, port 0
–
–10
μ
A
I
CC
Power supply current (see Figure 27):
Active mode @ 1.8 V V
CC
/ 1 MHz
Active mode @ 1.8 V V
CC
/ 12 MHz
Active mode @ 3.3 V V
CC
/ 12 MHz
Idle mode @ 1.8 V V
CC
1 MHz
Idle mode @ 1.8 V V
CC
12 MHz
Idle mode @ 3.3 V V
CC
12 MHz
Power-down mode (see Figure 32 for
conditions)
Internal reset pull-down resistor
Pin capacitance
8
(except EA)
–
–
–
–
–
–
–
0.15
1.35
2.70
0.1
0.25
0.5
0.4
1.5
3.7
0.24
0.68
0.68
2
mA
mA
mA
mA
mA
mA
μ
A
T
amb
= 0
°
C to 70
°
C
1
R
RST
C
IO
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In
such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can
exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 V specification when the
address bits are stabilizing.
4. See Figures 29 through 32 for I
CC
test conditions.
Active mode:
I
CC
= fclk *0.1 mA/MHz + 0.3 mA (1.8 V). See Figure 27
Active mode:
I
CC
= fclk *0.25 mA/MHz + 0.7 mA (3.3 V)
Idle mode:
I
CCI
= fclk *0.04 mA/MHz + 0.2 mA
5. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
10 mA
Maximum I
per 8-bit port:
20 mA
Maximum total I
for all outputs:
40 mA
If I
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
7. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
8. Pin capacitance is characterized but not tested. Pin capacitance is less than 15 pF.
40
225
k
–
15
pF
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