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參數(shù)資料
| 型號： | P87CL52X2BBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family |
| 中文描述： | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44 |
| 文件頁數(shù)： | 6/47頁 |
| 文件大?。?/td> | 301K |
| 代理商： | P87CL52X2BBD |
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Philips Semiconductors
Product data
P87CL52X2/54X2
80C51 8-bit microcontroller family
8K/16K OTP 256 bytes RAM ROMless low voltage
(1.8 V to 3.3 V), low power, high speed (33 MHz)
2003 May 14
6
PIN DESCRIPTIONS
PIN NUMBER
LQFP
16
38
37–30
MNEMONIC
V
SS
V
CC
P0.0–0.7
TSSOP
9
29
28–21
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0 V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins
that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I
IL
). Alternate
functions for Port 1 include:
T2 (P1.0):
Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction control
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I
). Port 2 emits
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source
current because of the pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves
the special features of the 80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
1
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
1
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
CC
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable:
The read strobe to external program memory. When the
P87CL5xX2 is executing code from the external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
P1.0–P1.7
40–44,
1–3
30–37
I/O
40
41
30
31
I/O
I
I/O
P2.0–P2.7
18–25
10–17
P3.0–P3.7
5,
7–13
1–6
I/O
5
7
8
9
10
11
12
13
4
1
2
I
O
I
I
I
I
O
O
I
3
4
5
6
38
RST
ALE
27
19
O
PSEN
26
18
O
EA/V
PP
29
20
I
XTAL1
15
8
I
XTAL2
NOTE:
To avoid “l(fā)atch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
CC
+ 0.5 V or V
SS
– 0.5 V, respectively.
1. Absent in the TSSOP38 package.
14
7
O
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