參數(shù)資料
型號(hào)： P87CL52X2BBD
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family
中文描述： 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44
文件頁(yè)數(shù)： 36/47頁(yè)
文件大?。?/td> 301K
代理商： P87CL52X2BBD
Philips Semiconductors
Product data
P87CL52X2/54X2
80C51 8-bit microcontroller family
8K/16K OTP 256 bytes RAM ROMless low voltage
(1.8 V to 3.3 V), low power, high speed (33 MHz)
2003 May 14
36
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C V
CC
= 3.3 V
±
10%, V
SS
= 0 V
1, 2, 3
VARIABLE CLOCK
4
12 MHz to f
max
MIN
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
33 MHz CLOCK
MIN
21
5
SYMBOL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the P87CL5xX2 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 12 MHz to 33 MHz. For frequencies equal or less than 12 MHz, see 12 MHz
“AC Electrical Characteristics”, page 35.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20
μ
s for power-on or wakeup from power down.
FIGURE
20
20
20
20
20
20
20
20
20
20
20
PARAMETER
MAX
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
4t
CLCL
–65
55
t
CLCL
–25
3t
CLCL
–45
5
45
3t
CLCL
–60
30
0
0
t
CLCL
–25
5t
CLCL
–80
10
5
70
10
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
22
21, 22
21, 22
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6t
CLCL
–100
6t
CLCL
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5t
CLCL
–90
60
0
0
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
90
105
140
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
45
0
5
80
0
0
55
t
CLCL
–25
t
CLCL
+25
5
24
24
24
24
High time
Low time
Rise time
Fall time
0.38t
CLCL
0.38t
CLCL
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
5
ns
ns
ns
ns
23
23
23
23
23
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
167
ns
ns
ns
ns
ns
0
10t
CLCL
–165
138
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