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參數(shù)資料
| 型號(hào)： | P82C150AHT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 22 PIN R/A MALE PRESSFIT ATCA ZONE 1 CON |
| 中文描述： | 1 CHANNEL(S), 125K bps, LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 209K |
| 代理商： | P82C150AHT |
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1996 Jun 19
15
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with
digital and analog port functions
P82C150
7.3.2
T
RANSMISSION OF
D
ATA
F
RAMES
Data Frames transmitted by the P82C150 contain three
data bytes (see Fig.7). The first data byte contains the
status information and the register address A3 to A0 (see
Tables 8 and 9), the other two data bytes contain the
content of the addressed I/O Register.
After each successful message transmission, the
P82C150 delays the transmission of a possibly further
pending message for three bit times. The reason is to give
other CAN controllers - with a lower identifier priority - the
possibility to transmit a message in case of faulty contact
at one of the edge-triggered port pins.
7.3.3
R
ECEPTION OF
D
ATA
F
RAMES AND
R
EMOTE
F
RAMES
Received Data Frames have the same format as
transmitted ones, only the DIR-bit (ID.0) in the Arbitration
Field is different. The status bits RSTD, EW, BM1 and BM0
are ignored during reception.
The P82C150 confirms each reception of a Data Frame by
transmitting a Data Frame containing the (new) contents of
the addressed I/O Register.
7.3.3.1
Exceptions to the rule
1.
Analog Configuration Register: If a P82C150 receives
a Data Frame addressing the Analog Configuration
Register and the ADC bit is set to logic 1, it will
respond with two messages. The first message returns
the contents of the Analog Configuration Register. The
control instructions are executed (e.g. next analog
input channel selected), and an analog-to-digital
conversion cycle is started after a set-up time. After
finishing the analog-to-digital conversion cycle, the
second message is transmitted containing the result
(ADC Register).
2.
ADC Register: On receiving a Data Frame addressing
the ADC Register, the P82C150 starts an
analog-to-digital conversion cycle. It automatically
returns the result of the conversion (ADC Register) by
transmitting a respective Data Frame after finishing
the analog-to-digital conversion cycle.
At normal operation, the calibration messages are
confirmed by returning a dominant bit in the
acknowledge slot. There is no particular confirmation
message returned by the P82C150. Only after
entering the calibrated state (start-up), a Data Frame
(‘sign-on’ message) containing the Data Input Register
contents is transmitted indicating to the host node, that
the P82C150 is now ready for transmission.
3.
7.3.3.2
Remote Frame
Received Remote Frames must have the Data Length
Code DLC = 3 (Remote Frames with DLC
≠
3 are ignored).
It is answered by a Data Frame containing the contents of
the Data Input Register.
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