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參數(shù)資料
| 型號： | P80L42 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 0.833 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大小： | 305K |
| 代理商： | P80L42 |
UPI-C42/UPI-L42
Table 4. UPI Instruction Set
(Continued)
Mnemonic
Description
Bytes
Cycles
CONTROL
(Continued)
*
SUSPEND
Invoke Suspend Power-
down mode
No Operation
1
2
NOP
1
1
REGISTERS
INC Rr
INC
@
Rr
Increment register
Increment data
memory
Decrement register
1
1
1
1
DEC Rr
1
1
SUBROUTINE
CALL addr
RET
RETR
Jump to subroutine
Return
Return and restore
status
2
1
1
2
2
2
FLAGS
CLR C
CPL C
CLR F0
CPL F0
CLR F1
CPL F1
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
1
1
1
1
1
1
1
1
1
1
1
1
Mnemonic
Description
Bytes
Cycles
BRANCH
JMP addr
JMPP
@
A
DJNZ Rr, addr
Jump unconditional
Jump indirect
Decrement register
and jump
Jump on Carry
e
1
Jump on Carry
e
0
Jump on A Zero
Jump on A not Zero
Jump on T0
e
1
Jump on T0
e
0
Jump on T1
e
1
Jump on T1
e
0
Jump on F0 Flag
e
1
Jump on F1 Flag
e
1
Jump on Timer Flag
e
1, Clear Flag
Jump on IBF Flag
e
0
Jump on OBF Flag
e
1
Jump on Accumula-
for Bit
2
1
2
2
2
2
JC addr
JNC addr
JZ addr
JNZ addr
JT0 addr
JNT0 addr
JT1 addr
JNT1 addr
JF0 addr
JF1 addr
JTF addr
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
JNIBF addr
2
2
JOBF addr
2
2
JBb addr
2
2
*
UPI-C42/UPI-L42 Only.
REVISION SUMMARY
The following has been changed since Revision
-003:
1. Delete all references to standby power down
mode.
The following has been changed since Revision
-002:
1. Added information on keyboard controller prod-
uct family.
2. Added I
HI
specification for the UPI-L42.
The following has been changed since Revision
-001:
1. Added UPI-L42 references and specification.
25
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