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參數(shù)資料
| 型號： | P4C198-35PM |
| 廠商： | Pyramid Semiconductor Corporation |
| 英文描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 中文描述： | 超高速16K的× 4靜態(tài)CMOS五羊 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 244K |
| 代理商： | P4C198-35PM |
1
Document #
SRAM113
REV A
Revised October 2005
P4C198/P4C198L, P4C198A/P4C198AL
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
5V ± 10% Power Supply
Data Retention, 10
μ
A Typical Current from 2.0V
P4C198L/198AL (Military)
Output Enable & Chip Enable Control Functions
– Single Chip Enable P4C198
– Dual Chip Enable P4C198A
Common Inputs and Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 28-Pin 350 x 550 mil LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C198/L and P4C198A/L are 65,536-bit ultra high-
speed static RAMs organized as 16K x 4. Each device
features an active low Output Enable control to eliminate
data bus contention. The P4C198/L also have an active
low Chip Enable (the P4C198A/L have two Chip Enables,
both active low) for easy system expansion. The CMOS
memories require no clocks or refreshing and have equal
access and cycle times. Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance
power supply. Data integrity is maintained with supply
DESCRIPTION
voltages down to 2.0V. Current drain is typically 10
μ
A
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin
300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC
packages providing excellent board level densities.
DIP (P4, C4, D4),
SOJ (J4)
P4C198 (P4C198A)
LCC (L5)
P4C198 (P4C198A)
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