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參數(shù)資料
| 型號(hào)： | P4C1258-25PI |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM |
| 中文描述： | 64K X 4 STANDARD SRAM, 25 ns, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 185K |
| 代理商： | P4C1258-25PI |
P4C1258
Page 5 of 9
Document #
SRAM123
REV OR
12. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED)
(9)
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
Parameter
-15
-20
-25
-35
Unit
Min
Min
Min
Min
Max
Max
Max
Max
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
DW
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
13
12
12
0
12
0
7
0
2
6
20
15
15
0
15
0
8
0
2
8
25
18
18
0
18
0
10
0
2
35
25
25
0
25
0
15
0
3
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
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