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參數(shù)資料
| 型號(hào)： | P4C1256L-70PILF |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDIP28 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 1155K |
| 代理商： | P4C1256L-70PILF |
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W39L040
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6.4 Write Operation Status
6.4.1 DQ7: Data Polling
The W39L040 device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequences. For sector erase, the Data Polling is valid after the last rising edge of the sector
erase #WE pulse. Data Polling must be performed at sector addresses within any of the sectors being
erased. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously
while the output enable (#OE) is asserted low. This means that the device is driving status information
on DQ7 at one instant of time and then that byte
′s valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –
DQ6 may be still invalid. The valid data on DQ0
DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, or sector erase time-out (see "Command Definitions").
6.4.2 DQ6: Toggle Bit
The W39L040 also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For sector/page erase, the
Toggle Bit is valid after the last rising edge of the sector/page erase #WE pulse. The Toggle Bit is
active during the sector/page erase time-out.
Either #CE or #OE toggling will cause DQ6 to toggle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P4C1256L-70SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L-70SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L70SNCLF | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L70SNILF | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1257-20CC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
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