
L
G
R
Analog to Digital Converter
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
148
Analog to Digital Converter
MOTOROLA
12.6.2 A/D Data Register
One 8-bit result register is provided. This register is updated each time
COCO is set.
12.7 A/D During WAIT Mode
The A/D converter continues normal operation during WAIT mode. To
decrease power consumption during WAIT, it is recommended that both
the ADON and ADRC bits in the A/D status/control register be cleared if
the A/D converter is not being used. If the A/D converter is in use and
the system clock rate is above 1.0 MHz, it is recommended that the
ADRC bit be cleared.
NOTE:
As the A/D converter continues to function normally in WAIT mode, the
COCO bit is not cleared.
12.8 Analog Input
The external analog voltage value to be converted by the A/D converter
is sampled on an internal capacitor through a resistive path provided by
input-selection switches and a sampling aperture time switch. Sampling
time is limited to 12 bus clock cycles. After sampling, the analog value is
stored on a capacitor and held until the end of conversion. During this
hold time, the analog input is disconnected from the internal A/D system
and the external voltage source sees a high impedance input.
The equivalent analog input during sampling is a RC low-pass filter with
resistance around 50 K
and a capacitance of around 10pF. (It should
be noted that these are typical values measured at room temperature).
$004E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset:
U
U
U
U
U
U
U
U
Figure 12-2. A/D Data Register (ADDR)