
L
G
R
Serial Peripheral Interface (SPI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
122
Serial Peripheral Interface (SPI)
MOTOROLA
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See
Figure 10-1
.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of simply as inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. Refer to
Figure 10-1
.
SPR1, SPR0 — SPI Clock Rate Selects
If the device is a master, the two serial peripheral rate bits select one
of four division ratios of the input-clock to be used as SCK (see
Table 10-1
). These bits have no effect in slave mode.
Bit 6 (SPP = SPI Prescaler) of the SCI baud rate register,
Section 11.8.5 Baud Rate Register (BAUD)
, determines the input
clock of the SPI module.
SPP — SPI Prescaler
1 = SCI receiver clock connected to the SPI clock input
0 = bus clock connected to the SPI clock input
NOTE:
If SPP is set, the SPI clock rate is dependent on the SCI clock rate. The
SPI clock rate is given by E: PRS1: PRS2: PRS0. PRS1 and PRS2 are
Table 10-1. SPI Clock Rate Selection
SPR1
SPR0
Input clock divided by PRS0
0
0
2
0
1
4
1
0
16
1
1
32