Chapter 19 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
709
19.3.1.11.1
Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map
Read: Anytime
Write: Anytime when DBG not armed.
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
ADDRESS HIGH
ADDRESS MEDIUM
ADDRESS LOW
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
DATA HIGH MASK
DATA LOW MASK
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
0x0028
7
0
6
5
4
3
2
1
0
R
W
NDB
TAG
BRK
RW
RWE
SRC
COMPE
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 19-13. Debug Comparator Control Register (Comparators A and C)
0x0028
7
6
5
4
3
2
1
0
R
W
SZE
SZ
TAG
BRK
RW
RWE
SRC
COMPE
Reset
0
0
0
0
0
0
0
0
Figure 19-14. Debug Comparator Control Register (Comparators B and D)
Table 19-27. DBGXCTL Field Descriptions
Field
Description
7
(COMPB/D)
SZE
Size Comparator Enable Bit
— The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
(COMPA/C)
NDB
Not Data Bus Compare
— The NDB bit controls whether the match occurs when the data bus matches the
comparator register value or when the data bus differs from the register value. Furthermore database bits can
be individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Table 19-26. Comparator Register Layout