Chapter 6 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
189
6.3.1.1
XGATE Control Register (XGMCTL)
All module level switches and flags are located in the module control register
Figure 6-3
.
Read: Anytime
Write: Anytime
15
0
14
0
XG
FRZM
0
13
0
XG
DBGM
0
12
0
XG
SSM
0
11
XG
10
0
9
0
8
0
7
6
5
4
3
2
0
1
0
R
W
XGEM
XGE
XGFRZ XGDBG XGSS XGFACT
XG
SWEIF
XGIE
FACTM
0
SXG
0
Reset
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-3. XGATE Control Register (XGMCTL)
Table 6-1. XGMCTL Field Descriptions (Sheet 1 of 3)
Field
Description
15
XGEM
XGE Mask
— This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is
written to the XGEM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGE in the same bus cycle
1 Enable write access to the XGE in the same bus cycle
14
XGFRZM
XGFRZ Mask
— This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared
if a "1" is written to the XGFRZM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGFRZ in the same bus cycle
1 Enable write access to the XGFRZ in the same bus cycle
13
XGDBGM
XGDBG Mask
— This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared
if a "1" is written to the XGDBGM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGDBG in the same bus cycle
1 Enable write access to the XGDBG in the same bus cycle
12
XGSSM
XGSS Mask
— This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a
"1" is written to the XGSSM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGSS in the same bus cycle
1 Enable write access to the XGSS in the same bus cycle