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參數(shù)資料
| 型號： | P2041AG-08ST |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, SOIC-8 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 177K |
| 代理商： | P2041AG-08ST |
November 2006
P2041A
rev 0.2
Versatile EMI Reduction IC
3 of 8
Notice: The information in this document is subject to change without notice.
Spread spectrum selection
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest
without affecting system performance. The spreading is described as a percentage deviation of the center frequency
( Note: the center frequency is the frequency of the external reference input on XIN/CLK, Pin 1).
Example of a typical printer or scanner application that operates on a clock frequency of 40MHz:
A spreading selection of SR1=1 and SR0=1 provides a percentage deviation of +/-1.00%* (see Table 1) of Center
Frequency. This results in the frequency on ModOUT being swept from 40.40MHz to 39.60MHz at a modulation rate of
(40/40)*34.72 = 34.72KHz (see Table 1). This particular example (see Figure below) given here is a common EMI reduction
method for scanners and has already been implemented by most of the leading manufacturers.
NOTE: Spreading range selection varies from different system manufacturers and their designs. The spreading range of P2041A can be set to +/-2.5% when
working with certain scanner model.
P2041A Application Schematic for Flat-Bed Scanner
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, VIN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
TSTG
Storage temperature
-65 to +125
°C
TA
Operating temperature
-40 to +85
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
TDV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
1
2
3
4
8
7
6
5
VDD
SR0
ModOUT
SSON
VSS
SR1
XOUT
XIN/CLK
P2041A
VDD
Modulated 40MHz signal with ± 1.00%
Deviation
and
modulation
rate
of
34.72KHz. This signal is connected back
to the clock crystal Input pin of the
system ASIC.
NOTE: The above schematic indicates
The exact setting of this example:
Default setting (no connection on pin 3,
7 and 5)
40MHz
0.1F
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相關(guān)代理商/技術(shù)參數(shù) |
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