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參數(shù)資料
| 型號： | P2041AG-08ST |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, SOIC-8 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 177K |
| 代理商： | P2041AG-08ST |
November 2006
P2041A
rev 0.2
Versatile EMI Reduction IC
2 of 8
Notice: The information in this document is subject to change without notice.
SSON
ModOUT
Pin Configuration
Pin Description
Pin#
Pin Name
Type
Description
1
XIN/CLK
I
Connect to crystal or externally generated clock signal.
2
XOUT
I
Connect to crystal. No connect if externally generated clock signal is used.
3
SR1
I
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
4
VSS
P
Ground Connection. Connect to system ground.
5
SSON
I
Digital logic input used to enable Spread Spectrum function (Active Low). Spread
Spectrum function enable when low. This pin has an internal pull-low resistor.
6
ModOUT
O
Spread Spectrum Clock Output.
7
SR0
I
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
8
VDD
P
Connect to +3.3V or +5.0V
Spread Range Selection
SR1
SR0
Spreading Range
Modulation rate
0
+/- 1.50%
(Fin/40)*34.72 KHz
0
1
+/- 2.50%
(Fin/40)*34.72 KHz
1
0
+/- 0.50%
(Fin/40)*34.72 KHz
1
+/- 1.00%
(Fin/40)*34.72 KHz
XOUT
SR0
1
2
3
4
5
6
7
8
P2040C
XIN/CLK
SR1
VSS
VDD
1
2
3
4
5
6
7
8
P2041A
SR1
VDD
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