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參數(shù)資料
| 型號(hào)： | P14827EJ1V0AN00 |
| 英文描述： | uPB1005K RF/IF Down-Converter+PLL Frequency Synthesizer ICs for GPS Receivers |
| 中文描述： | uPB1005K射頻/中頻下變頻器鎖相環(huán)頻率合成器的GPS接收機(jī) |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 188K |
| 代理商： | P14827EJ1V0AN00 |
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8
Preliminary Application Note P14822EJ2V0AN
3. INTERNAL CIRCUIT CONFIGURATION
The
μ
PC8172TB is a double-balanced mixer + bias circuit IC. The
μ
PC8187TB has the same circuit configuration
as other up-converter ICs (apart from the absence of a power-save control circuit), but features a high IP
3
due to
optimization of the current distribution and adjustment of the CG and IIP
3
. Figure 3-1 shows the internal equivalent
circuit diagram.
This IC includes bypass capacitors for double balanced mixer type complementary IF inputs in order to improve the
AC characteristics of the 50 MHz to 400 MHz IF frequency range. This lowers the conversion gain when the IF input
frequency is lower than the minimum frequency. When the IF input frequency is higher than the maximum frequency,
the conversion gain is lowered according to the frequency characteristics of the internal transistors.
The RF output pin is an open collector, and since there is no on-chip component that limits the lower limit of the
frequency range, the user should provide an external narrow-band matching circuit for the internal transistors'
frequency characteristic range (800 MHz to 2.5 GHz) to set the desired bandwidth.
Since this mixer has been designed as a product for frequency up-converters, the user's determination of the
desired bandwidth should be made according to the following conditions. Note with caution that this mixer's design
and operation as a frequency down-converter are not guaranteed (other frequency down-converter mixer ICs are
available).
Frequency condition: | f
RFout
– f
LOin
| = f
IFin
, f
RFout
, f
LOin
> f
IFin
Figure 3-1. Internal Equivalent Circuit Diagram
PS
LOinput
GND
IFinput
RFoutput
V
CC
Q3
Q4
Q1
Q2
Q5
Q6
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