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參數(shù)資料
| 型號(hào)： | P14827EJ1V0AN00 |
| 英文描述： | uPB1005K RF/IF Down-Converter+PLL Frequency Synthesizer ICs for GPS Receivers |
| 中文描述： | uPB1005K射頻/中頻下變頻器鎖相環(huán)頻率合成器的GPS接收機(jī) |
| 文件頁數(shù)： | 4/23頁 |
| 文件大小： | 188K |
| 代理商： | P14827EJ1V0AN00 |
4
Preliminary Application Note P14822EJ2V0AN
CONTENTS
1.
PREFACE..........................................................................................................................................
5
2.
PRODUCT OVERVIEW....................................................................................................................
2.1
Product Overview....................................................................................................................
2.2
Manufacturing Process...........................................................................................................
2.3
Differences with the Existing Product...................................................................................
5
5
6
7
3.
INTERNAL CIRCUIT CONFIGURATION........................................................................................
8
4.
EXTERNAL CIRCUIT CONFIGURATIONS....................................................................................
4.1
Impedance Matching at RF Output........................................................................................
4.2
Input Impedance Matching.....................................................................................................
4.3
Bypass Capacitor....................................................................................................................
9
9
9
9
5.
APPLICATION CHARACTERISTICS .............................................................................................. 16
5.1
Operation Rise/Fall Times ...................................................................................................... 16
6.
CONCLUSION................................................................................................................................... 20
Precautions for design-ins
(1) Observe precautions for handling because of electro-static sensitive devices.
(2) Form a ground pattern as widely as possible to minimize ground impedance. All the ground pins must be
connected as shortly as possible to decrease impedance difference (to prevent malfunction or undesired
oscillation).
(3) The bypass capacitor should be attached to the V
CC
pin.
(4) The RF output pin connects parallel inductors of an external LC matching circuit to V
CC
to apply a bias and RF
load.
(5) A DC cut capacitor must be each attached to the input pins and external adjustment of pin voltages is prohibited
for input pins.
See the product's data sheet for more detailed caution points and descriptions of electrical specifications.
μ
PC8172TB Data Sheet (Document No.: P14729E)
μ
PC8187TB Data Sheet (Document No.: P15106E)
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