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參數(shù)資料
| 型號： | P12611EJ1V0AN00 |
| 英文描述： | MCU CMOS 28 LD 20MHZ 8K FLASH, -40C to +85C, 28-SOIC 300mil, TUBE |
| 中文描述： | uPB1509GV 1 GHz的輸入除以2。 4。 8預(yù)分頻器集成電路便攜式無線電系統(tǒng) |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 110K |
| 代理商： | P12611EJ1V0AN00 |
3
2.3 Internal Circuit
Figure 2-3 shows the internal circuit configuration of the
μ
PB1509GV. The input stage includes an on-chip
amplifier for securing high sensitivity and the output stage amplifier for maintaining a sufficient output level, which
both realize a wide operation range. The frequency divider section consists of three master-slave T-type flip-flop
circuits, each dividing its input frequency by two.
Each block operates as follows. Each flip-flop in the
μ
PB1509GV divides its input frequency at each falling edge
of the input signal from the IN pin (rising edge with the
μ
PB587G). The first stage flip-flop (Divider 1) performs the
divide by 2 operation all the time, while the other two flip-flops are enabled or disabled by the SW1 and SW2 control
signals. When SW1 or SW2 is connected to the V
CC1
line, the respective flip-flop passes on its input to the next
stage; when SW1 or SW2 is connected to GND or left unconnected, it divides its input by 2 and passes on the result
to the next stage, which allows users to select a frequency divide ratio from among 2, 4, and 8 according to the
combination of these control signals. The amplifier of the output stage is of the emitter-follower configuration and
provides a stable output level little influenced by the load impedance. For details, refer to
3.2 Load Impedance and
Characteristics
.
Figure 2-3. Internal Block Diagram of
μ
PB1509GV
D
CLK
Divider 1
Divider 2
Divider 3
IN
IN
GND
Q
Q
D
CLK
Q
Q
D
CLK
Q
Q
V
CC1
SW1
SW2
V
CC2
OUT
RF flow
Input
amplifier
Output
amplifier
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