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3 P
IN
D
ESCRIPTIONS
Data Sheet Rev 1.1
Page 5
OXFW911
OXFORD SEMICONDUCTOR LTD.
1394 PHY-LINK interface
104, 105, 108, 109, 110, 111, 114,
115
116,117
119
121
102
103
ARM external interface
2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 16,
17, 18, 19, 20, 24
35, 36, 37, 38, 41, 42, 43, 44, 45,
46, 49, 50, 51, 52, 53, 54, 60
123, 124, 27, 33
Dir
1
Name
Description
I/O
PD[7:0]
Phy-Link Data Bus
I/O
I
O
IU
O
CTL[1:0]
PHYCLK
LREQ
LINKON
LPS
Phy-Link Control Bus
49.152 MHz clock sourced by PHY
Link Request
Requests link to power up when in a low power mode
Indicates to phy that link is powered and ready
T_I/O
D[15:0]
ARMexternal data bus
T_O
A[16:0]
ARMexternal address bus
T_O
CS#[3:0]
ARMexternal chip selects. CS0#is always used for program
ROM.
ARMexternal output enable. Active when reading data from
external devices including programROM
Write Enable. Active when writing to external devices
External ARMinterrupt
28
T_O
OE#
34
61
T_O
T_IU
WE#
INT#
IDE interface
86, 82, 80, 78, 74, 72, 70, 66, 65,
69, 71, 73, 77, 79, 81, 85
99, 97, 98
101, 100
T_I/O
ID[15:0]
IDE data bus
T_O
T_O
IA[2:0]
ICS#[1:0]
IDE address bus
IDE chip select. Used to select the Command Block or
Control Block registers.
IDE output enable. Only used when external buffering is
required to drive IDE data bus
IDE interface reset
IDE interface write strobe
IDE interface read strobe
63
T_O
IDE_OE#
64
89
90
91
92
95
62
T_O
T_I
T_O
T_O
T_O
T_O
T_I
IRESET
DMARQ
DIOW#
DIOR#
IORDY
DMACK#
INTRQ
EEPROMinterface
125
126
127
58
O
O
O
GPO1
GPO2
GPO3
GPI
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Input
T_IU
Miscellaneous Pins
56
128
IU
T_O
I
RESET#
CKOUT
TEST_SEL,
TEST[1:0]
UIF
Global reset for the OXFW911. Active Low.
Clock output. 49.152 MHz clock output.
‘100’ = NORMAL OPERATION. Other settings are for
foundry test purposes only.
Leave unconnected to use internal Flash, tie low to use only
external device
22, 32, 31
57
IU
Power and ground
2
15, 8, 40, 48, 59, 76, 94, 107, 113
30, 21, 23, 68, 84, 88, 120
VDD
VDD
AC VDD
DC VDD
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state