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參數(shù)資料
| 型號： | OXFW900 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IEEE1394 to ATA/ATAPI Native Bridge |
| 中文描述： | IEEE1394連接到ATA / ATAPI的母語橋 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大小： | 187K |
| 代理商： | OXFW900 |
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Data Sheet Revision 1.0
Page 10
OXFW900
OXFORD SEMICONDUCTOR LTD.
Symbol
Parameter
Mode 0
min
240
Mode 0
max
Mode 1
min
160
Mode1
max
Mode 2
min
120
Mode 2
max
Units
t2cyc
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(fromdata bus being valid until
STROBE edge )
Data valid hold time at sender (from
STROBE edge until data may
become invalid
First STROBE time (for device to
first negate DSTROBE fromSTOP
during a data-in burst)
Limted interlock time
Interlock time with mnimum
Unlimted interlock time
Maximumtime allowed for output
drivers to release (frombeing
asserted or negated)
Mnimumdelay time required for
output drivers to assert or negate
(fromreleased state)
Envelope time ( fromDMACK#to
STOP and HDMARDY#during
data-out burst initiation
STROBE to DMARDY time ( refer
to ATA spec
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long
after
the
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate pause
after negating DMARDY#)
Pull-up time before allowing IORDY
to be released
Mnimumtime a device shall wait
before driving IORDY
Setup and hold times for DMACK#
(before assertion or negation )
Time fromSTROBE edge to
negation of DMARQ or assertion of
STOP (when sender termnates a
burst )
ns
tcyc
114
75
55
ns
t2cyc
235
156
117
ns
tds
tdh
tdvs
15
5
70
10
5
48
7
5
34
ns
ns
ns
tdvh
6
6
6
ns
tfs
0
230
0
200
0
170
ns
tli
tmi
tui
taz
0
20
0
150
10
0
20
0
150
10
0
20
0
150
10
ns
ns
ns
ns
tzah
tzad
20
0
20
0
20
0
ns
tenv
20
70
20
70
20
70
ns
tsr
20
25
25
ns
trfs
negation
of
75
60
50
ns
trp
160
125
100
ns
tiordyz
20
20
20
ns
tziordy
0
0
0
ns
tack
20
20
20
ns
tss
50
50
50
ns
Table 7: OXFW900 Ultra DMA timings
相關PDF資料 |
PDF描述 |
|---|---|
| OXFW900-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OZ6812 | ACPI CardBus Controller |
| OZ6812B | ACPI CardBus Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OXFW900-TQ-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911PLUS | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:1394A-to-ATA7/ATAPI Bridge |
| OXFW911-TQ-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW912 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:1394B-to-ATA7/ATAPI Bridge |
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