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參數(shù)資料
| 型號： | OV7620 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | OV7620 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA |
| 中文描述： | OV7620的單芯片CMOS VGA彩色數(shù)碼相機 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大?。?/td> | 313K |
| 代理商： | OV7620 |
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OV7620 Product Specifications - Rev. 1.2 (5/13/00)
OMNIVISION TECHNOLOGIES INC.
39
Preliminary
Company Confidential
U
6-U0: U channel digital output offset adjustment. Range: +128mV ~ -128mV. If register 27 bit 2=0, this
register will be updated by internal auto A/D BLC circuit, and write a value to this register with
SCCB has no effect. If register 27 bit 2=1, U channel offset adjustment will use the register
stored value which can be changed by SCCB. If register 26 bit 1=1, this register has no effect
to A/D output data. If output RGB raw data, this register will adjust R/G/B data.
U7: Offset adjustment direction: 0 - Add U[6:0]; 1 -Subtract U[6:0].
If register 2D bit 0 = 0, this register has no function.
Register 23- rw: Crystal Current control.
CC7 - CC6: Crystal amplifier current gain. (00) maximum current; (11) minimum current
CC5 ~ CC0: Reserved
Register 24- rw: AEW Auto Exposure White Pixel Ratio
Registers 24 and 25 together control the AEC target values for image brightness.
For a brighter image, increase register 24 and decrease register 25.
For a darker image, decrease register 24 and decrease reister 25.
AEW7-AEW0 - used to calculate the white pixel ratio. OV7620 AEC algorithm counts the whole field/frame
white pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level
is lower than a fixed level) number. When white/black pixel ratio is same as the ratio defined
by registers [25] and [26], image stable. This register is used to define the white pixel ratio,
default is 25%, each LSB represent step: Interlaced: 1.3%; Progressive Scan: 0.7%. Change
range is: Interlaced: [01] ~ [4A]; Progressive Scan: [01] ~ [96]. Increase AEW<7:0> will
increase the white pixel ratio. For same light condition, the image brightness will increase if
AEW<7:0> increase.
Note: AEW<7:0> must combined with register [26] AEB<7:0>. Keep the relation always true: AEW<7:0> +
AEB<7:0> > [4A] for Interlaced; AEW<7:0> + AEB<7:0> > [90].
Register 22- rw: U Channel Offset Adjustment
Bits
U7
U6
U5
U4
U3
U2
U1
U0
Default
1
0
0
0
0
0
0
0
Bits
CC7
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Default
0
0
0
-
-
-
-
-
Bits
AEW7
AEW6
AEW5
AEW4
AEW3
AEW2
AEW1
AEW0
Interlace
0
0
0
0
1
0
0
0
Progressive Scan
0
0
0
1
0
0
0
0
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