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參數(shù)資料
| 型號： | OV5017 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single chip 1/4 video image sensor |
| 中文描述： | 單芯片1 / 4的視頻圖像傳感器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 138K |
| 代理商： | OV5017 |
October 20, 1997
Version 1.6
3
OV5017
Confidential Preliminary Product Specification
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
Pin Type and Default Level:
I: digital input, floating, I-1: digital input, with 100k pull up, I-0: digital input, with 100k pull down, OD: digital CMOS level output, OA: analog
CMOS, level output, XI/XO: xtal IO, K: analog input, Q: 75
output, FT: factory test, Bias: power supply bias
22
I
WEB
Write enable input for the internal registers. When the chip is selected (CSB = 0),
external data is latched into the registers with the rising edge of WEB.
23
I
CSB
Chip select for the device. CSB = 0 selects the device.
24, 25
OD
XCLKI,
XCLKO
Crystal oscillator in/out pins. Nominal clock frequency is 14.31MHz for CCIR 50 Hz
timing. The maximum pixel rate is limited to one half of the clock frequency. To
connect an external clock to XCLKI, leave XCLKO open.
26
OD
HREF
Horizontal timing reference output. Asserted high during every valid line for the
duration of the valid window width. The window sizing function affects the number
of valid lines in a frame as well as the number of valid pixels in a line. HREF and
status(1), are identical valid pixel timing information.
27
OD
PCLK
Pixel clock output. Defaulted to be a continuous clock. Can be programmed via the
internal register to be on during the valid pixel window only. Video data at output
bus (D0-D7) is updated with the rising edge of PCLK and is guaranteed to be valid
at the falling edge of PCLK.
28
OD
VSYNC
Vertical timing reference output. It is high once per frame for the duration of the
vertical sync period. VSYNC and status (2) are identical vertical sync timing
information.
29
Bias
DVDD
Digital power (+5V) connection.
30
Bias
DGND
Digital ground. Connect to supply common
31
Bias
OGND
Digital output ground. Connect to supply common
32-39
OD
D0-D7
Bi-directional data bus for video output data and internal register read/write
operations.
40
Bias
OVDD
Digital output power (+5V/+3.3V) connection.
41
Bias
ZVDD
Analog power (+5V) connection.
42
Bias
VR2
Internal reference voltage. Requires a 0.1uF external capacitor to AGND.
43
Bias
ZGND
Analog ground. Connect to supply common.
44
Bias
DEGND
Decoder ground. Connect to supply common.
45
Bias
DEVDD
Decoder power (+5V) connection.
47
Bias
VVDD
Video output power (+5V) connection.
48
Q
AVO
Composite video output. It is capable of driving 150
load, Vp-p is 2.0 V.
Table 1.Pin Descriptions (Continued)
Pin #
Class
Pin Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OV5116N | OV5116N SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT |
| OV6120 | SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
| OV6620 | SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
| OV6130 | SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OV5116N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OV5116N SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT |
| OV5116P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:B/W | PAL | 352 x 288 | ANALOG | CameraChip |
| OV530-BT10 | 制造商:Omni Vision 功能描述: |
| OV5620 | 制造商:OMNIVISION 制造商全稱:OMNIVISION 功能描述:advanced digital imaging and HD video |
| OV6120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
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