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參數(shù)資料
| 型號： | OV5017 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single chip 1/4 video image sensor |
| 中文描述： | 單芯片1 / 4的視頻圖像傳感器 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 138K |
| 代理商： | OV5017 |
OV5017
2
Version 1.6
October 20, 1997
Confidential Preliminary Product Specification
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
The Image Core is a complete analog video camera with 384 x 288 pixel size, which can run at full video
speed. The analog video signal complies with CCIR standards. At 50 fps, it may be too fast for many
applications; therefore, the frame rate or pixel rate can be programmed to match the external system
requirements. The on-chip 8-bit A/D can convert the video signal at 50 fps, and the conversion is syn-
chronized with the actual pixel rate.
The OV5017 also outputs standard timing reference signals such as VSYNC, HREF, PCLK. Databus is
shared by negating OEB
.
The exposure control can be set to auto or manual operation. Automatic exposure computation is based
on full size image array and an exposure range over 100X. The AGC operation is tied to AEC in auto
operation. Therefore, use automatic exposure control when selecting full image size. Manual exposure
control allows individually adjusting exposure and gain based on actual application. Therefore, use man-
ual exposure time if the window is smaller than full size or if the target object is brighter or darker than
the average background.
The frame rate divider can achieve various frame rates on the fly without changing the input clock fre-
quency.
Single frame operation provides one frame data transfer by controlling the assertion of HREF for one
complete frame period. Setting FCTL(7) signals the control to assert the HREF in the next frame. Clear-
ing this bit before the new frame cancels the assertion of HREF.
Table 1.Pin Descriptions
Pin #
Class
Pin Name
Description
1
Bias
SGND
Sensor ground. Connect to supply common.
2
Bias
SVDD
Sensor power (+5V) connection.
3
Bias
AVDD
Analog power (+5V) connection.
4
I-0
FSI
External frame sync input. A rising edge on FSI sets the chip vertical sync timing.
For proper operation, the frequency of FSI must be half of the programmed frame
rate. Internally pulled down with a 100k resistor. Leave open or ground if unused.
5
Bias
VrCR
Internal reference voltage. Requires a 0.1uF external capacitor to AGND.
6
Bias
AGND
Analog ground. Connect to supply common.
7
Bias
AGND
Analog ground. Connect to supply common.
8-17
FT
N/C
Factory test. Leave open.
18, 19,
20, 46
I
A3-A0
Address inputs for internal the registers. Requires CSB = 0 to access the registers.
21
I
OEB
Output enable for the eight bit data bus. OEB = 0 enables the data bus drivers.
OEB = 1 puts the data bus in tristate.
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