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參數(shù)資料
| 型號(hào)： | ORT8850 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip(現(xiàn)場(chǎng)可編程系統(tǒng)芯片) |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（現(xiàn)場(chǎng)可編程系統(tǒng)芯片） |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 153K |
| 代理商： | ORT8850 |
2
Lucent Technologies Inc.
Preliminary Product Brief
May 2000
ORCA ORT8850 FPSC
Embedded Core Features (Serial)
I
Implemented in an ORCA Series 4 FPGA array.
I
Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
I
No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz—106 MHz
clock, and a frame pulse.
I
High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without exter-
nal clocks.
I
Eight-channel HSI function provides 850 Mbits/s
serial interface per channel for a total chip bandwidth
of 6.8 Gbits/s (full duplex).
I
HSI function uses Lucent Technologies Microelec-
tronics Group's 850 Mbits/s serial interface core.
Rates from 212 Mbits/s to 850 Mbits/s are supported
directly (Lower rates directly supported through deci-
mation and interpolation).
I
LVDS I/Os compliant with EIA*-644, support hot
insertion. All embedded LVDS I/Os include both input
and output on-board termination to allow long-haul
driving of backplanes.
I
Low-power HSI core.
I
Low-power LVDS buffers.
I
Programmable STS-1, STS-3, and STS-12 framing.
I
Independent STS-1, STS-3, and STS-12 data
streams per quad channels.
I
8:1 data multiplexing/demultiplexing for 106.25 MHz
byte-wide data processing in FPGA logic.
I
On-chip, phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T recommendation
G.958.
I
Powerdown option of HSI receiver on a per-channel
basis.
I
Selectable 8B/10B coder/decoder or SONET scram-
bler/descrambler.
I
HSI automatically recovers from loss-of-clock once
its reference clock returns to normal operating state.
I
Frame alignment across multiple ORT8850 devices
for work/protect switching at OC-192/STM-64 and
above rates.
I
In-band management and configuration through
transport overhead extraction/insertion.
I
Supports transparent mode where the only insertion
is A1/A2 framing bytes.
I
Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
I
Built-in boundry scan (IEEE
1149.1 JTAG).
I
FIFOs align incoming data across all eight channels,
two groups of four channels or four groups of two
channels. Optional ability to bypass alignment
FIFOs.
I
1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for pro-
tection switching applications. STS-192 and above
rates are supported through multiple devices.
I
ORCAFPGA soft intellectual property core support
for a variety of applications.
I
Programmable STM pointer mover bypass mode.
I
Programmable STM framer bypass mode.
I
Programmable inverted data framing per channel.
I
Programmable CDR bypass mode (clocked LVDS
high-speed interface).
I
Redundant outputs and multiplexed redundant inputs
for CDR I/Os allow for implementation of eight chan-
nels with redundancy on a single device.
Embedded Core Features (Parallel)
I
Three full-duplex, double data rate (DDR) I/O groups
include 8-bit data, 1 control, and 1 clock. Each inter-
face is implemented with LVDS I/Os that include on-
board termination to allow long-haul driving of back-
planes, such as the industry standard RapidIO nter-
face.
I
External I/O speeds on DDR interface up to
311 MHz (622 Mbits/s per pin), with internal, single-
edge data transferred at 1/2 rate on a 32-bit bus plus
control.
I
Automatic centering of transmit clock in data eye for
DDR interface.
I
Direct interfaces to Lucent Pi-Sched (266 MHz DDR
LVDS), Pi-X (128 MHz TTL), and APC (100 MHz
TTL) ATM/IP switch/port controller devices.
* EIAis a registered trademark of Electronic Industries Association.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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