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參數(shù)資料
| 型號(hào)： | ORT4622 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip (FPSC) Four Channel x 622 Mbits/s Backplane Transceiver(現(xiàn)場(chǎng)可編程系統(tǒng)芯片（四通道x 622 M位/秒背板收發(fā)器）) |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器（現(xiàn)場(chǎng)可編程系統(tǒng)芯片（四通道x 622 M位/秒背板收發(fā)器）） |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 146K |
| 代理商： | ORT4622 |
4
Lucent Technologies Inc.
Product Brief
May 2000
Four Channel x 622 Mbits/s Backplane Transceiver
ORCA ORT4622 FPSC
FPSC Highlights
I
Implemented as an embedded core in the ORCA
Series 3+ FPSC architecture.
I
Allows the user to integrate the core with up to 120K
gates of programmable logic (all in one device) and
provides up to 242 user I/Os in addition to the
embedded core I/O pins.
I
FPGA portion retains all of the features of the ORCA
Series 3 FPGA architecture:
— High-performance, cost-effective, 0.25 μm, 5-level
metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, as well as for a general-
purpose interface to the FPGA. Glueless interface
to i960
and PowerPC
processors with user-
configurable address space provided.
* PALis a trademark of Advanced Micro Devices, Inc.
i960is a registered trademark of Intel Corporation.
PowerPCis a registered trademark of International Business
Machines Corporation.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex
functions, such as digital phase-locked loops,
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True internal 3-state, bidirectional buses with
simple control provided by the SLIC.
— 32 x 4 RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
High-speed on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
Software Support
I
Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with the
embedded core functions.
I
Embedded core configuration options and simulation
netlists generated by the FPSC Configuration Man-
ager utility.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ORT4622BC432-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT551 | 制造商:Hasco Components International Corp 功能描述: |
| ORT551(1315) | 制造商:OKI Semiconductor 功能描述: |
| ORT551/10-15 AT | 功能描述:磁性/簧片開(kāi)關(guān) 1 Form C 14mm AT 1015 OKI RoHS:否 制造商:MEDER electronic (Standex) 開(kāi)關(guān)類(lèi)型:Reed 觸點(diǎn)形式:1 Form A (SPST-NO) 觸點(diǎn)額定值:10 VA 操作范圍:10 At to 50 At 工作間隙: 磁鐵類(lèi)型: 顏色: 端接類(lèi)型:Axial 封裝:Bulk |
| ORT551-1/10-15 AT | 功能描述:磁性/簧片開(kāi)關(guān) 1 Form C 14mm AT1015 Formed Ld OKI RoHS:否 制造商:MEDER electronic (Standex) 開(kāi)關(guān)類(lèi)型:Reed 觸點(diǎn)形式:1 Form A (SPST-NO) 觸點(diǎn)額定值:10 VA 操作范圍:10 At to 50 At 工作間隙: 磁鐵類(lèi)型: 顏色: 端接類(lèi)型:Axial 封裝:Bulk |
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