參數(shù)資料
型號(hào): ORLI10G-1BMN416I
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝: PLASTIC, MULTILAYER, BGA-416
文件頁數(shù): 33/74頁
文件大?。?/td> 1411K
代理商: ORLI10G-1BMN416I
Agere Systems Inc.
39
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Transmit (Line)/Receive (System) STS-48/STS-192 (2.5G/10G) Data Outputs
Figure 20 illustrates the timing for the transmit (line)/receive (system) STS-48/STS-192 data stream. Both the clock
and data pins are driven with low-voltage differential signal buffers. The expected clock rate is 622.08 MHz/
666.51428 MHz and the receive/transmit data is clocked out on the rising edge of the clock. In 2.5G mode, each of
the four channesl uses one set of TX_CLK_OUT_n with four TX_DAT_OUT_n data pins. In 10G mode, only
TX_CLK_OUT[0] is used with the 16 TX_DAT_OUT pins. The timing values for the diagram are given in Table 14.
5-9089.c (F)
Figure 20. Transmit (Line)/Receive (System) Data Timing
Table 14. Transmit (Line)/Receive (System) Data Output Timing
Symbol
Parameter
Min
Typ
Max
Unit
t4
Clock Period
1608/1500
ps
Duty Cycle1
1. This requirement is for all sources of the output clocks (e.g., RCLKSI, etc.).
45
50
55
%
t5
Data Delay from Clock Edge
–220
220
ps
t6
Data Rise Time: 20%—80%
100
200
ps
t7
Data Fall Time: 80%—20%
100
200
ps
Clock In to Clock Out
1500
4500
ps
t5
TX_DAT_OUT[15:0]
P
N
P
N
t6
t7
TX_CLK_OUT[0]
t4
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