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| 型號(hào)： | OR3T55-4PS208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 182/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T55-4PS208 |
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Lucent Technologies Inc.
73
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Programmable Clock Manager (PCM):
Advance Information (continued)
2x Clock Duty-Cycle Adjustment
A doubled-frequency, duty-cycle adjusted version of
the input clock can be constructed in DLL mode. The
first clock cycle of the 2x clock output occurs when the
input clock is high, and the second cycle occurs when
the input clock is low. The duty cycle can be adjusted in
1/32 (6.25%) increments of the input clock period.
Additionally, each of the two doubled-clock cycles that
occurs in a single input clock cycle may be adjusted to
have different duty cycles. DLL 2x clock mode is
selected by setting bit 4 of register five to a 0, and by
setting register six, bits [5:4] to 01 for ExpressCLK out-
put, and/or bits [7:6] to 01 for system clock output. The
duty-cycle percentage value is entered in register
three. See register three programming details for more
information. Duty-cycle values where both cycles of the
doubled clock have the same duty cycle are also
shown in Table 28.
Phase-Locked Loop (PLL) Mode
The PLL mode of the PCM is used for clock multiplica-
tion and clock delay minimization functions. PLL func-
tions make use of the PCM dividers and use feedback
signals, often from the FPGA array. The use of feed-
back is discussed with each PLL submode. PLL mode
is selected by setting bit 0 of register five to 1.
Clock Delay Minimization
PLL mode can be used to minimize the effects of the
input buffer and input routing delay on the clock signal.
PLL mode causes the feedback clock to align in phase
with the input clock (refer back to the block diagram in
Figure 45) so that the delay between the input clock
and a clock that is fed back to the PCM is effectively
eliminated.
There is a dedicated feedback path from an adjacent
middle CLKCNTRL block to the PCM. Using the corner
ExpressCLK
pad as the input to the PCM and using this
dedicated feedback path, the clock from the Express-
CLK
output of the PCM, as viewed at the CLKCNTRL
block, will be phase-aligned with the ExpressCLK input
to the PCM. These relationships are diagrammed in
A feedback clock can also be input to the PCM from
general routing. This allows for compensating for delay
between the PCM input and a point in the general rout-
ing. The use of this routed-feedback path is not gener-
ally recommended. Because compensation is based
on the programmable routing, the amount of clock
delay compensation can vary between FPGA lots and
fabrication processes, and will vary each time that the
feedback line is routed using different resources. Con-
tact Lucent Technologies for application notes regard-
ing the use of routed-feedback delay compensation.
Figure 47. ExpressCLK Delay Minimization
Using the PCM
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values
Register 3 [7:0]
7 6 5 4 3 2 1 0
Duty Cycle
(%)
0 0 0 0 0 0 0 0
6.25
0 0 0 0 1 0 0 1
12.50
0 0 0 1 0 0 1 0
18.75
0 0 0 1 1 0 1 1
25.00
0 0 1 0 0 1 0 0
31.25
0 0 1 0 1 1 0 1
37.50
0 0 1 1 0 1 1 0
43.75
0 0 1 1 1 1 1 1
50.00
1 1 0 0 0 0 0 0
56.25
1 1 0 0 1 0 0 1
62.50
1 1 0 1 0 0 1 0
68.75
1 1 0 1 1 0 1 1
75.00
1 1 1 0 0 1 0 0
81.25
1 1 1 0 1 1 0 1
87.50
1 1 1 1 0 1 1 0
93.75
5-5980(F)
CORNER
ExpressCLK AT
CLKCNTRL
DELAY
DELAY IS COMPENSATED
AT PCM INPUT
OUTPUT OF PCM
OUTPUT WITHOUT
USING PCM
OUTPUT
ExpressCLK
USING PCM
ExpressCLK
COMPENSATION EQUALS DELAY
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| OR3T80-4PS208I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| OR3T55-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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