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參數(shù)資料
| 型號： | OR3T306S240I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP-240 |
| 文件頁數(shù)： | 171/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T306S240I-DB |
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Lattice Semiconductor
7
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Description (continued)
ispLEVER Development System
The ispLEVER Development System is used to pro-
cess a design from a netlist to a congured FPGA. This
system is used to map a design onto the
ORCA archi-
tecture and then place and route it using ispLEVER’s
timing-driven tools. The development system also
includes interfaces to, and libraries for, other popular
CAE tools for design entry, synthesis, simulation, and
timing analysis.
The ispLEVER Development System interfaces to
front-end design entry tools and provides the tools to
produce a congured FPGA. In the design ow, the
user denes the functionality of the FPGA at two points
in the design ow: at design entry and at the bit stream
generation stage.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter-
mine device speed and a back-annotated netlist can be
created to allow simulation. Timing and simulation out-
put les from ispLEVER are also compatible with many
third-party analysis tools. Its bit stream generator is
then used to generate the conguration data which is
loaded into the FPGA’s internal conguration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Com-
bined with the front-end tools, ispLEVER produces
conguration data that implements the various logic
and routing options discussed in this data sheet.
Architecture
The
ORCA Series 3 FPGA comprises three basic ele-
ments: PLCs, PICs, and system-level functions. Figure
1 shows an array of programmable logic cells (PLCs)
surrounded by programmable input/output cells (PICs).
Also shown are the interquad routing blocks (hIQ, vIQ)
present in Series 3. System-level functions (located in
the corners of the array) and the routing resources and
conguration RAM are not shown in Figure 1.
The OR3T55 array in Figure 1 has PLCs arranged in
an array of 18 rows and 18 columns. The location of a
PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
located on all four sides of the FPGA between the
PLCs and the device edge. PICs are indicated using
PT and PB to designate PICs on the top and bottom
sides of the array, respectively, and PL and PR to des-
ignate PICs along the left and right sides of the array,
respectively. The position of a PIC on an edge of the
array is indicated by a number, counting from left to
right for PT and PB and top to bottom for PL and PR
PICs.
Each PIC contains routing resources and four program-
mable I/Os (PIOs). Each PIO contains the necessary
I/O buffers to interface to bond pads. PIOs in Series 3
FPGAs also contain input and output FFs, fast open-
drain capability on output buffers, special output logic
functions, and signal multiplexing/demultiplexing capa-
bilities.
PLCs comprise a programmable function unit (PFU), a
supplemental logic and interconnect cell (SLIC), and
routing resources. The PFU is the main logic element
of the PLC, containing elements for both combinatorial
and sequential logic. Combinatorial logic is done in
look-up tables (LUTs) located in the PFU. The PFU can
be used in different modes to meet different logic
requirements. The LUT’s twin-quad architecture pro-
vides a congurable medium-/large-grain architecture
that can be used to implement from one to eight inde-
pendent combinatorial logic functions or a large num-
ber of complex logic functions using multiple LUTs. The
exibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
gate count per PFU while increasing system speed.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4- or 5-input
logic function and many multilevel logic functions using
ORCA’s softwired LUT (SWL) connections. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| OR3T30-7BA256 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T307BA256-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1568 LUT 221 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T30-7BA256I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T30-7BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T30-7BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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