
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Lucent Technologies Inc.
29
Programmable Logic Cells (continued)
Figure 20. Multiple PLC View of Inter-PLC Routing
5-5767(F)
PFU
hxH[9:0]
hx1[9:0]
hCLK
hx1[9:0]
hx5[9:0]
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
hx1[9:0]
hx5[9:0]
hxL[9:0]
hx1[9:0]
hx5[9:0]
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
vx1L[9:
0]
vx5[9:0
]
vCLK
vxH[9:0]
vx1[9:0
]
vxL[9:0
]
vx5[9:0
]
vCLK
vxH[9:0]
vxL[9:0
]
vx5[9:0
]
vx1[9:0
]
vCLK
vxH[9:0]
vx1[9:0
]
vx1[9:0
]
vx1[9:0
]
vx1
[9:0]
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
SLIC
PLC BOUNDARY
2 OF 10
LINE-BY-LINE
10
2
KEY: CONFIGURABLE SIGNAL-LINE BREAKS: