參數(shù)資料
型號： OR2T40B
廠商： Lattice Semiconductor Corporation
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場可編程門陣列
文件頁數(shù)： 48/192頁
文件大小： 935K
代理商： OR2T40B
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48
Lattice Semiconductor
Data Sheet
January 2002
ORCA
Series 2 FPGAs
FPGA Configuration Modes
(continued)
Master Serial Mode
In the master serial mode, the FPGA loads the con
fi
gu-
ration data from an external serial ROM. The con
fi
gura-
tion data is either loaded automatically at start-up or on
a
PRGM
command to recon
fi
gure. The ATT1700 and
ATT1700A Series can be used to con
fi
gure the FPGA
in the master serial mode. This provides a simple 4-pin
interface in an 8-pin package. The ATT1736, ATT1765,
and ATT17128 serial ROMs store 32K, 64K, and 128K
bits, respectively.
Con
fi
guration in the master serial mode can be done at
powerup and/or upon a con
fi
gure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET
/OE and
CE
inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be con
fi
gured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a con
fi
gure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple con
fi
guration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the
CLOCK input of the serial ROM. During the con
fi
gura-
tion process, CCLK clocks one data bit on each rising
edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the
RESET
/OE and
CE
of the serial
ROM(s). There are several methods for enabling the
serial ROM’s
RESET
/OE and
CE
inputs. The serial
ROM's
RESET
/OE is programmable to function with
RESET active-high and
OE
active-low or
RESET
active-
low and OE active-high.
In Figure 41, serial ROMs are cascaded to con
fi
gure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's
PRGM
input. The
FPGA’s
INIT
input is connected to the serial ROM’s
RESET
/OE input, which has been programmed to
function with
RESET
active-low and OE active-high.
The FPGA DONE is routed to the
CE
pin. The low on
DONE enables the serial ROMs. At the completion of
con
fi
guration, the high on the FPGA's DONE disables
the serial ROM.
Serial ROMs can also be cascaded to support the con-
fi
guration of multiple FPGAs or to load a single FPGA
when con
fi
guration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the
fi
rst serial ROM is read, the serial ROM outputs
CEO
low and 3-states the DATA output. The next serial
ROM recognizes the low on
CE
input and outputs con-
fi
guration data on the DATA output. After con
fi
guration
is complete, the FPGA’s DONE output into
CE
disables
the serial ROMs.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple con
fi
gura-
tion programs. In these applications, the next
con
fi
guration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous con
fi
guration program. The reason the interface in
Figure 41 will not work in this application is that the low
output on the
INIT
signal would reset the serial ROM
address pointer, causing the
fi
rst con
fi
guration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During con
fi
guration, DIN receives
con
fi
guration data, and after con
fi
guration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in
ORCA
Foundry) may correct the problem.
An alternative is to use
LDC
to drive the serial ROM's
CE
pin. In order to reduce noise, it is generally better to
run the master serial con
fi
guration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Figure 41. Master Serial Configuration Schematic
ATT1700A
DIN
M2
M1
M0
ORCA
SERIES
FPGA
CCLK
DOUT
TO DAISY-
CHAINED
DEVICES
DATA
CLK
CE
CEO
ATT1700A
DATA
CLK
RESET/OE
CEO
CE
TO MORE
SERIAL ROMs
AS NEEDED
DONE
INIT
PROGRAM
RESET/OE
PRGM
5-4456.1(F)
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OR2T40B7BC352-DB 制造商:Rochester Electronics LLC 功能描述:- Bulk
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