
Data Sheet
June 1999
ORCA Series 2 FPGAs
164
Lucent Technologies Inc.
Timing Characteristics
(continued)
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram
Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: V
DD
= 5.0 V ± 5%, 0 °C
≤
T
A
≤
70 °C; OR2CxxA Industrial: V
DD
= 5.0 V ± 10%, –40 °C
≤
T
A
≤
+85 °C.
OR2TxxA Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
≤
T
A
≤
70 °C; OR2TxxA Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
≤
T
A
≤
+85
°C.
Parameter
Symbol
T
S
T
H
T
CH
T
CL
F
C
T
D
Min
20
0
50
50
—
—
Max
—
—
—
—
10
30
Unit
ns
ns
ns
ns
MHz
ns
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics
OR2TxxB Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
≤
T
A
≤
70 °C; OR2TxxB Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
≤
T
A
≤
+85
°C.
Parameter
Symbol
T
S
T
H
T
CH
T
CL
F
C
T
D
Min
15
0
12.5
12.5
—
—
Max
—
—
—
—
40
10
Unit
ns
ns
ns
ns
MHz
ns
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
5-4534(F)
CCLK
INIT
D[7:0]
DOUT
RDY
0
1
2
3
4
BYTE 0
BYTE 1
T
INIT_CLK
T
CH
T
CL
T
H
T
S
T
D
5
6
7
0