參數(shù)資料
型號(hào)： OR2T04A-3S208
廠商： Electronic Theatre Controls, Inc.
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 64/192頁(yè)
文件大小： 3148K
代理商： OR2T04A-3S208
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64
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 2 FPGAs
Estimating Power Dissipation
(continued)
OR2T15A Clock Power
P
= [0.34 mW/MHz
+ (0.17 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T15A clock power
≈
5.9 mW/MHz.
OR2T26A Clock Power
P
= [0.35 mW/MHz
+ (0.19 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T26A clock power
≈
8.3 mW/MHz.
OR2T40A Clock Power
P
= [0.37 mW/MHz
+ (0.23 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T40A clock power
≈
12.4 mW/MHz.
The power dissipated in a PIC is the sum of the power
dissipated in the four I/Os in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each I/O depends on
whether it is configured as an input, output, or input/
output. If an I/O is operating as an output, then there is
a power dissipation component for P
IN
, as well as
P
OUT
. This is because the output feeds back to the
input.
The power dissipated by an input buffer (V
IH
= V
DD
–
0.3 V or higher) is estimated as:
P
IN
= 0.09 mW/MHz
The 5 V tolerant input buffer feature dissipates addi-
tional dc power. The dc power, P
TOL
, is always dissi-
pated for the OR2TxxA, regardless of the number of
5 V tolerant input buffers used when the V
DD
5 pins are
connected to a 5 V supply as shown in Table 16. This
power is not dissipated when the V
DD
5 pins are con-
nected to the 3.3 V supply.
Table 16. dc Power for 5 V Tolerant I/Os for
OR2TxxA deviced
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
P
OUT
= (C
L
+ 8.8 pF) x V
DD
2
x F Watts
where the unit for C
L
is farads, and the unit for F is Hz.
As an example of estimating power dissipation,
suppose that a fully utilized OR2T15A has an average
of three outputs for each of the 400 PFUs, that all
20 clock branches are used, that 150 of the 400 PFUs
have FFs clocked at 40 MHz (16 of which are operating
in a synchronous memory mode), and that the PFU
outputs have an average activity factor of 20%.
Twenty inputs, 32 outputs driving 30 pF loads, and
16 bidirectional I/Os driving 50 pF loads are also gen-
erated from the 40 MHz clock with an average activity
factor of 20%. The worst-case (V
DD
= 3.6 V) power dis-
sipation is estimated as follows:
P
PFU
= 400 x 3 (0.08 mW/MHz x 20 MHz x 20%)
= 384 mW
P
CLK
= [0.34 mW/MHz + (0.17 mW/MHz – Branch)
(20 Branches)
+ (0.01 mW/MHz – PFU) (150 PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(16 SMEM_PFUs)] [40 MHz]
= 212 mW
P
IN
= 20 x [0.09 mW/MHz x 20 MHz x 20%]
= 7 mW
P
TOL
= 3.4 mW
P
OUT
= 30 x [(30 pF + 8.8 pF) x (3.6)
2
x 20 MHz
x 20%]
= 60 mW
P
BID
= 16 x [(50 pF + 8.8 pF) x (3.6)
2
x 20 MHz
x 20%]
= 49 mW
TOTAL
= 0.72 W
Device
2T04A
2T06A
2T08A
2T10A
2T12A
2T15A
2T26A
2T40A
P
TOL
(V
DD
5 = 5.25 V)
1.7 mW
2.0 mW
2.4 mW
2.7 mW
3.0 mW
3.4 mW
4.0 mW
5.0 mW
相關(guān)PDF資料
PDF描述
OR2T04A-3S208I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 100pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
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