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| 型號(hào)： | OR2T04A-3PS160 |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 58/192頁(yè) |
| 文件大小： | 3148K |
| 代理商： | OR2T04A-3PS160 |
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Data Sheet
June 1999
ORCA Series 2 FPGAs
58
Lucent Technologies Inc.
Special Function Blocks
(continued)
Boundary-Scan Cells
Figure 51 is a diagram of the boundary-scan cell (BSC)
in the ORCA series PICs. There are four BSCs in each
PIC: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR. The
BSC controls the functionality of the in, out, and 3-state
signals for each pad.
The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an out-
put buffer receives input from the PLC array and pro-
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (P_IN), output
(P_OUT), and 3-state (P_TS) signals at the pads. The
BSC consists of two circuits: the bidirectional data cell
is used to access the input and output data, and the
direction control cell is used to access the 3-state
value. Both cells consist of a flip-flop used to shift scan
data which feeds a flip-flop to control the I/O buffer. The
bidirectional data cell is connected serially to the direc-
tion control cell to form a boundary-scan shift register.
The TAPC signals (capture, update, shiftn, treset, and
TCK) and the MODE signal control the operation of the
BSC. The bidirectional data cell is also controlled by
the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirec-
tional data cell receives input buffer data into the BSC.
When HOLI is high, the BSC is loaded with functional
data from the PLC.
The MODE signal is generated from the decode of the
instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output
buffer. When the MODE signal is low (BYPASS or
SAMPLE), functional data from the FPGA’s internal
logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is
provided for each device in the ORCA series of FPGAs.
The BSDL is generated from a device profile, pinout,
and other boundary-scan information.
5-2844(F).r4
Figure 51. Boundary-Scan Cell
D
Q
D
Q
D
Q
D
Q
SCAN IN
P_OUT
HOLI
BIDIRECTIONAL DATA CELL
I/O BUFFER
DIRECTION CONTROL CELL
MODE
UPDATE/TCK
SCAN OUT
TCK
SHIFTN/CAPTURE
P_TS
P_IN
PAD_IN
PAD_TS
PAD_OUT
0
1
0
1
0
1
0
1
0
1
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