參數(shù)資料
型號: OQ2535HP
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字傳輸電路
英文描述: SDH/SONET STM16/OC48 multiplexer(SDH/SONET STM16/OC48多路復(fù)用器)
中文描述: MUX/DEMUX, PQFP100
封裝: 14 X 14 X 1.40 MM, PLASTIC, SOT-470-1, HLQFP-100
文件頁數(shù): 2/20頁
文件大小: 95K
代理商: OQ2535HP
1999 Oct 04
2
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
FEATURES
Normal and loop (test) modes
3.3 V TTL compatible data inputs
Differential Current-Mode Logic (CML) clock and data
outputs
5 V TTL clock output (low speed interface)
High input sensitivity (100 mV for the high speed clock
input)
Boundary Scan Test (BST) at low speed interface, in
accordance with “IEEE Std 1149.1-1990”
Low power dissipation (typically 1.65 W).
GENERAL DESCRIPTION
The OQ2535HP is a 32-channel multiplexer intended for
use in STM16/OC48 applications. It combines data from a
total of 32
×
78 Mbits/s input channels onto a single
2.5 Gbits/s output channel. It features 3.3 V TTL data
inputs and a 5 V TTL clock output at the low speed
interface, and CML compatible inputs and outputs at the
high speed interface.
ORDERING INFORMATION
BLOCK DIAGRAM
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
OQ2535HP
HLQFP100
plastic heat-dissipating low profile quad flat package; 100 leads;
body 14
×
14
×
1.4 mm
SOT470-1
handbook, full pagewidth
MGK351
4
ENL
SYNSEL1
SYNSEL2
TRST
TMS
TCK
TDI
TDO
CDIV
DOUT
DOUTQ
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CIN
CINQ
DIOA
DIOC
CLOOPQ
clock
4 : 1 MUX
SYNCHRONIZATION
DIVIDE BY 4
622 MHz
OQ2535HP
78 MHz
2.5 GHz
BAND GAP
REFERENCE 2
BAND GAP
REFERENCE 1
DIVIDE BY 8
B
4
×
8 : 1 MUX
622 Mbits/s
2.5 Gbits/s
78
Mbits/s
load
pulse
2
5
3
7
6
58
59
62
32
13
10
78
5
14, 37,
63, 85, 86
VDD
4
12, 39,
87, 88
VEE
60
VCC
VCC(T)
BGCAP2
BGCAP1
31
(2)
(1)
GND
16
REFC2
38
REFC1
61
90
91
82
83
65
66
68
69
71
72
74
75
D0
to
D31
Fig.1 Block diagram.
(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100.
相關(guān)PDF資料
PDF描述
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