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參數(shù)資料
| 型號(hào)： | OQ2535HP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SDH/SONET STM16/OC48 multiplexer(SDH/SONET STM16/OC48多路復(fù)用器) |
| 中文描述： | MUX/DEMUX, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-470-1, HLQFP-100 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 95K |
| 代理商： | OQ2535HP |
1999 Oct 04
13
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
TIMING
Typical values at T
amb
= 25
°
C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
Notes
1.
The set-up and hold times given are valid for SYNSEL1 = SYNSEL2 = HIGH. Different SYNSEL1, SYNSEL2
combinations will produce different set-up and hold times (see Table 3).
All CML outputs must be terminated externally with 50
to GND. The specified timing characteristics are applicable
in both normal and loop modes.
2.
Table 3
Timing relationship between the clock edge and the data valid region (minimum values)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TTL input timing
f
clk(CDIV)
t
r(CDIV)
, t
f(CDIV)
CDIV rise/fall time
t
su
input data set-up time
t
h
input data hold time
CML output timing;
note 2
low speed output clock frequency
f
clk(CIN)
= 2.488 GHz
capacitive load of 15 pF
note 1
note 1
1200
2600
77.76
2600
MHz
ps
ps
ps
f
clk(COUT)
t
CDV
t
DI
t
r(CML)
, t
f(CML)
δ
COUT
output clock frequency
clock edge to data valid time
data invalid time
CML output rise/fall time
output clock duty factor
f
clk(CIN)
= 2.488 GHz
45
2.488
50
250
120
150
55
GHz
ps
ps
ps
%
SYNSEL2
SYNSEL1
t
su
1200
2800
1700
3300
t
h
UNIT
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
2600
1000
2100
500
ps
ps
ps
ps
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