參數(shù)資料
型號: OPTIMIZING
英文描述: CAN I/O Expander Family, -40C to +125C, 14-SOIC 150mil, T/R
中文描述: 優(yōu)化輸出Semtech公司雙極針驅(qū)動器(126k配置)
文件頁數(shù): 1/6頁
文件大?。?/td> 126K
代理商: OPTIMIZING
1
TEST AND MEASUREMENT PRODUCTS
www.semtech.com
PE-A2
Optimizing the Output Configuration of
Semtech Bipolar Pin Drivers
Revision 1 / December 18, 2002
Background: Connecting a Pin Driver to a Test Device
Ideally, the Driver output from a Driver/Comparator/Load
(DCL) IC would be connected to the Device Under Test
(DUT) pin with a perfect transmission line. The most
common connection scheme is for the DCL to be
impedance-matched to the transmission line while the
DUT end of the line is unterminated. In this case, the
driver waveform would be exactly reproduced at the DUT
and DUT waveforms would be perfectly reproduced at the
Comparator This perfect transmission line includes perfect
impedance matching at the DCL end as well as no parasitic
resistance, capacitance or inductance anywhere along the
line.
In practice, there are usually a number of things which
degrade the AC performance. For instance, if the source
impedance of the DCL is not perfectly matched to the
transmission line impedance, there will be amplitude errors
in the waveform. If the low frequency (real) portion of the
source impedance is incorrect, then there will be a step
in the waveform when driving an unterminated
transmission line, as shown in Figure 1.
If the real impedance is correctly matched, but there is a
capacitive or inductive mismatch (imaginary portion of the
source impedance), then there will be a glitch in the
waveform when driving an unterminated transmission line
as shown in Figure 2. This effect is greatest at the fastest
rise/fall times, so checking and optimizing this behavior
should be done at the fastest slew rates of interest.
Note that when the L-C balance is correct, the amount of
slowing of the rise/fall times caused by the impedance
mismatch is minimized. This can be seen by expanding
Figure 2 around the pulse rising edge as done in Figure 3.
The amount of improvement will be maximized for the
fastest rise/fall times.
Figure 1. Typical Waveforms When Driving a 3.3V Signal into a
50
Transmission Line with Varying DC Source Impedance
DC Impedance Matching
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
5.0
10.0
15.0
20.0
Time(ns)
R-out<50 ohms
R-out=50 ohms
R-out>50 ohms
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