參數(shù)資料
型號(hào)： OP635
廠商： Texas Instruments, Inc.
英文描述： Wideband, Single-Supply Operational Amplifier(寬帶,單電源運(yùn)算放大器)
中文描述： 寬帶，單電源運(yùn)算放大器（寬帶，單電源運(yùn)算放大器）
文件頁(yè)數(shù)： 16/18頁(yè)
文件大?。?/td> 284K
代理商： OP635
OPA634, OPA635
SBOS097A
16
intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
DISABLE OPERATION
The OPA635 provides a disable feature that may be used
either to reduce system power or to implement a simple
channel multiplexing operation. To disable, the control pin
must be asserted HIGH. Figure 7 shows a simplified internal
circuit for the disable control feature.
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but would, for resistive load
connected to mid-supply (V
S
/2), be at a maximum when the
output is fixed at a voltage equal to V
S
/4 or 3V
S
/4. Under this
condition, P
DL
= V
S2
/(16 R
L
), where R
L
includes feedback
network loading.
Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using
an OPA635 (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
°
C and driving a 150
load at mid-supply.
P
D
= 10V 13.5mA + 5
2
/(16 (150
|| 1500
)) = 144mW
Maximum T
J
= +85
°
C + (0.14W 150
°
C/W) = 107
°
C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA634 and OPA635 requires careful
attention to board layout parasitics and external component
types. Recommendations that will optimize performance
include:
a) Minimize parasitic capacitance
to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance
(<0.25") from the power-supply
pins to high frequency 0.1
μ
F decoupling capacitors. At the
device pins, the ground and power plane layout should not be
in close proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between the pins
and the decoupling capacitors. Each power-supply connec-
tion should always be decoupled with one of these capacitors.
An optional supply decoupling capacitor (0.1
μ
F) across the
two power supplies (for bipolar operation) will improve 2nd-
harmonic distortion performance. Larger (2.2
μ
F to 6.8
μ
F)
decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
50k
I
S
Control
V
DIS
+V
S
Q1
FIGURE 7. Simplified Disable Control Circuit (OPA635).
In normal operation, base current to Q1 is provided through
the 50k
resistor.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. Adding a simple RC filter into the DIS
pin from a higher speed logic line will reduce the glitch. If
extremely fast transition logic is used, a 1k
series resistor
will provide adequate bandlimiting using just the parasitic
input capacitance on the DIS pin while still ensuring ad-
equate logic level swing.
THERMAL ANALYSIS
Maximum desired junction temperature will set the maxi-
mum allowed internal power dissipation, as described be-
low. In no case should the maximum junction temperature
be allowed to exceed 175
°
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
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