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參數(shù)資料
| 型號： | OP635 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Wideband, Single-Supply Operational Amplifier(寬帶,單電源運算放大器) |
| 中文描述： | 寬帶，單電源運算放大器（寬帶，單電源運算放大器） |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 284K |
| 代理商： | OP635 |
OPA634, OPA635
SBOS097A
14
In the inverting configuration, three key design consider-
ation must be noted. The first is that the gain resistor (R
G
)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace, or other transmission line conductor), R
G
may be set equal to the required termination value and R
F
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R
G
to
50
for input matching eliminates the need for R
M
but
requires a 100
feedback resistor. This has the interesting
advantage of the noise gain becoming equal to 2 for a 50
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100
feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 200
to 1.5k
range. In this case, it is preferable to
increase both the R
F
and R
G
values, as shown in Figure 5,
and then achieve the input matching impedance with a third
resistor (R
M
) to ground. The total input impedance becomes
the parallel combination of R
G
and R
M
.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 5, the R
M
value
combines in parallel with the external 50
source imped-
ance (at high frequencies), yielding an effective driving
impedance of 50
|| 576
= 26.8
. This impedance is
added in series with R
G
for calculating the noise gain. The
resultant is 2.87 for Figure 5, as opposed to only 2 if R
M
could be eliminated as discussed above. The bandwidth will
therefore be lower for the gain of –2 circuit of Figure 5
(NG = +2.87) than for the gain of +2 circuit of Figure 1.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on the
non-inverting input (a parallel combination of R
T
= 750
).
If this resistor is set equal to the total DC resistance looking
out of the inverting node, the output DC error, due to the
input bias currents, will be reduced to (Input Offset Current)
times R
F
. With the DC blocking capacitor in series with R
G
,
the DC source impedance looking out of the inverting mode
is simply R
F
= 750
for Figure 5. To reduce the additional
high-frequency noise introduced by this resistor, and power-
supply feedthrough, R
T
is bypassed with a capacitor. As
long as R
T
< 400
, its noise contribution will be minimal.
As a minimum, the OPA634 and OPA635 require an R
T
value of 50
to damp out parasitic-induced peaking—a
direct short to ground on the non-inverting input runs the
risk of a very high-frequency instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
The OPA634 and OPA635 provide outstanding output volt-
age capability. Under no-load conditions at +25
°
C, the
output voltage typically swings closer than 140mV to either
supply rail; the guaranteed over temperature swing is within
300mV of either rail (V
S
= +5V).
The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V
BE
’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications, since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem, since most applications include a series
matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly to the
adjacent positive power-supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor in the
power-supply leads. This will, under heavy output loads,
reduce the available output voltage swing.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA634 and OPA635 can be very suscep-
tible to decreased stability and closed-loop response peaking
when a capacitive load is placed directly on the output pin.
When the primary considerations are frequency response
flatness, pulse response fidelity, and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load.
The Typical Performance Curves show the recommended
R
S
versus capacitive load and the resulting frequency re-
sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA634
and OPA635. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this value.
Always consider this effect carefully, and add the recom-
mended series resistor as close as possible to the output pin
(see Board Layout Guidelines section).
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