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| 型號： | OM11048 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 49/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD LPCXPRESSO LPC1343 |
| 產(chǎn)品培訓(xùn)模塊： | LPCXpresso |
| 標準包裝： | 1 |
| 系列： | LPCXpresso |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | LPC1343 |
| 所含物品： | 板，軟件 |
| 其它名稱： | 568-4947 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
53 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
10.5 I/O pins
[1]
Applies to standard port pins and RESET pin.
10.6 I2C-bus
[1]
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
Table 17.
Dynamic characteristics: I/O pins[1]
Tamb =
40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin configured as output
3.0
-
5.0
ns
tf
fall time
pin configured as output
2.5
-
5.0
ns
Table 18.
Tamb =
40 °C to +85 °C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
tf
fall time
of both SDA and SCL
signals
Standard-mode
-300
ns
Fast-mode
20 + 0.1
× Cb
300
ns
Fast-mode Plus
-
120
ns
tLOW
LOW period of the
SCL clock
Standard-mode
4.7
-
μs
Fast-mode
1.3
-
μs
Fast-mode Plus
0.5
-
μs
tHIGH
HIGH period of the
SCL clock
Standard-mode
4.0
-
μs
Fast-mode
0.6
-
μs
Fast-mode Plus
0.26
-
μs
tHD;DAT
data hold time
Standard-mode
0
-
μs
Fast-mode
0
-
μs
Fast-mode Plus
0
-
μs
tSU;DAT
data set-up time
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
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