參數(shù)資料
型號(hào)： OM11048
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 11/74頁(yè)
文件大小： 0K
描述： BOARD LPCXPRESSO LPC1343
產(chǎn)品培訓(xùn)模塊： LPCXpresso
標(biāo)準(zhǔn)包裝： 1
系列： LPCXpresso
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： LPC1343
所含物品： 板，軟件
其它名稱(chēng)： 568-4947
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
19 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
7.6.1 Features
Controls system exceptions and peripheral interrupts.
On the LPC1311/13/42/43, the NVIC supports up to 17 vectored interrupts. In
addition, up to 40 of the individual GPIO inputs are NVIC-vector capable.
8 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table.
Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.7 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC1311/13/42/43 use accelerated GPIO functions:
GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can
be achieved.
Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.8.1 Features
Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
Direction control of individual bits.
All I/O default to inputs with pull-up resistors enabled after reset with the exception of
the I2C-bus pins PIO0_4 and PIO0_5.
Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin.
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