參數(shù)資料
型號(hào)： OL2381AHN
廠商： NXP Semiconductors N.V.
元件分類： 微波射頻器件
英文描述： Highly Integrated Single Chip Sub 1-GHz RF Transceiver
封裝： OL2381AHN<SOT617-3 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-3.html<1<Always Pb-free,;
文件頁數(shù)： 18/43頁
文件大?。?/td> 2978K
代理商： OL2381AHN
AN11017
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Application note
Rev. 2 — 10 May 2011
18 of 43
NXP Semiconductors
AN11017
Transceiver OL2381 using wireless M-BUS
4.4 Port configuration
Writing to, and reading from OL2381 registers is always done through SPI ports (green
lines in
Figure 17
). The Host Controller is always clock master.
Sending and receiving RF data is done in this example through separate pins (blue lines
in
Figure 17
) and the OL2381 is always clock master.
The port register settings for this configuration are shown in the following sections.
Different configurations, such as working with a three wire interface, is explained in data
sheet
Ref. 1
, application note
Ref. 2
. It is recommended that the SPI controller hardware
is used to reduce processing load on the host controller, especially for data.
4.4.1
Port PORTCON0
The settings for register PORTCON0 are shown in
Figure 18
which represents the reset
condition for OL2381.
The data to the host controller can be inverted by setting bit P10INV to logic 1.
Table 16.
M-Bus radio link
Fig 17. SPI communication and separate TX/RX data, clock port and Interrupt pins
019aab769
MOSI
MISO
SCLK
Port1
Port2
Port3
Port4
HOST
CONTROLLER
OL2381
SDIO
P13/SDO
SCLK
SEN
P10/DATA
P12/CLOCK
P11/INT
Fig 18. Port configuration PORTCON0
M-Bus register PORTCON0 settings
OL2381 Register address
PORTCON0 (0x10)
0x28
Information
S, T, C, R, F
reset condition
019aab770
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