
5
Computation/Bit Manipulation Unit
The Computation/Bit Manipulation Unit (CBU) contains
three main elements:
The Computation Unit (CU)
The Bit Manipulation Unit (BMU).
The Saturation Unit, which is shared by the CU and the
BMU units.
Figure 3.
Computation and Bit Manipulation Unit Block Diagram
The CU consists of a 16- by 16-bit parallel 2s complement
multiplier, supporting single and double precision
multiplication, a 36-bit Arithmetical and Logical Unit (ALU)
and two 36-bit A-accumulators with access to the two
additional B-accumulators of the BMU. The OakDSPCore
can perform a single-cycle Multiply-Accumulate (MAC)
instruction, and has support for double precision
multiplication. A single-cycle division step is supported.
The Arithmetic Logic Unit (ALU) performs all arithmetic and
logical operations on data operands. It is a 36-bit, single-
cycle, non-pipelined unit. A maximum or minimum opera-
tion is available.
The BMU consists of a full 36-bit barrel shifter, a Bit-Field
Operation (BFO) unit, a special hardware (EXP) for
exponent calculation, and two 36-bit B-accumulators with
access to the two A-accumulators of the CU. Extension
nibbles of the B-accumulators offer protection against 32-
bit overflows. The Shift Value (SV) register is a 16-bit
register used for shifting operation and exponent
calculation.
Context switching (swapping) between the two sets of
accumulators is supported.
Saturation arithmetic is provided to selectively limit over-
flow from the high portion of an accumulator to the
extension bits. When necessary the saturation logic substi-
tutes a limited data value having maximum magnitude and
the same sign as the source accumulator.
Scaling Shifter
Multiplier
ALU
MUX
X
Y
P
Accumulator A0
Accumulator A1
Accumulator B0
Accumulator B1
Swap
Saturation Unit
EXP
SV
Barrel
Shifter
Bit Manipulation Unit
Computation Unit
Y Data Bus
X Data Bus
Bit Field
Operation