
3
Table 2.
Off-core Memory
Signal Name
Width
Description
Input/Output Signals
GEXDBP <15:0>
16
External data bus
Output Signals
PESRCN <5:0>
6
Source bus
PEDSTN <5:0>
6
Destination bus
DXAP <15:0>
16
Off-core XRAM address
PEDWP
1
Data write
PEDRP
1
Data read
Table 3.
Program Memory
Signal Name
Width
Description
Input Signals
BEXTPP
1
External program indication
Input/Output Signals
GIP <15:0>
16
Instruction data
Output Signals
PEXTIP
1
MOVP instruction indication
PPAP <15:0>
16
Program address
PPRP
1
Program read
PPWP
1
Program write
Table 4.
Direct Memory Access (DMA)
Signal Name
Width
Description
Input Signals
BFLOATDP
1
Float DXAP bus control
BFLOATPP
1
Float PPAP bus control
Output Signals
PRWEXTP
1
Read or write to/from external
registers
DOFCTRP
1
Off core data transaction
Table 5.
User I/O
Signal Name
Width
Description
Input Signals
BIUSER0P
1
User input 0
BIUSER1P
1
User input 1
Output Signals
CUSERO0P
1
User output 0
CUSERO1P
1
User output 1
Table 6.
Interrupts
Signal Name
Width
Description
Input Signals
LINT0P
1
Interrupt 0
LINT1P
1
Interrupt 1
LINT2P
1
Interrupt 2
LNMIP
1
Non-maskable Interrupt
Output Signals
PIACKN
1
Interrupt acknowledge
Table 7.
On-Chip Emulation Module (OCEM)
Signal Name
Width
Description
Input Signals
BTRAPREQP
1
TRAP interrupt
Output Signals
PSTATUSP
<3:0>
4
Internal status (used by the
OCEM module)
PTRAPAP
1
Trap active indication
PBKENDP
1
Block repeat end
DDTVMP
1
Data value match
PSFTP
1
Software trap indication
PDUMMYP
1
Dummy fetch (used by the
OCEM module)
Table 8.
System
Signal Name
Width
Description
Input Signals
PHI1
1
Phase1 Clock
PHI2
1
Phase2 Clock
LRSTP
1
Reset
BWAITP
1
Wait state indication
BBOOTP
1
BOOT indication
Table 5.
User I/O (Continued)
Signal Name
Width
Description