參數(shù)資料
型號(hào)： NT5SV8M8DT-7
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 190K
代理商： NT5SV8M8DT-7
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
17
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Clock and Clock Enable Parameters
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tCK3
Clock Cycle Time, CAS Latency = 3
6
1000
7
1000
7
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
7.5
1000
7.5
1000
10
1000
ns
tAC3 (A)
Clock Access Time, CAS Latency = 3
—
ns
1
tAC2 (A)
Clock Access Time, CAS Latency = 2
—
ns
1
tAC3 (B)
Clock Access Time, CAS Latency = 3
—
5.4
—
5.4
—
5.4
ns
2
tAC2 (B)
Clock Access Time, CAS Latency = 2
—
5.4
—
5.4
—
6
ns
2
tCKH
Clock High Pulse Width
2.5
—
2.5
—
3
—
ns
tCKL
Clock Low Pulse Width
2.5
—
2.5
—
3
—
ns
tCES
Clock Enable Set-up Time
1.5
—
1.5
—
2
—
ns
tCEH
Clock Enable Hold Time
0.8
—
0.8
—
1
—
ns
tSB
Power down mode Entry Time
0
6
0
7
0
7.5
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tCS
Command Setup Time
1.5
—
1.5
—
1.5
—
ns
tCH
Command Hold Time
0.8
—
0.8
—
0.8
—
ns
tAS
Address and Bank Select Set-up Time
1.5
—
1.5
—
1.5
—
ns
tAH
Address and Bank Select Hold Time
0.8
—
0.8
—
0.8
—
ns
tRCD
RAS to CAS Delay
15
—
15
—
20
—
ns
1
tRC
Bank Cycle Time
48
—
52
—
63
—
ns
1
tRAS
Active Command Period
36
100K
37
100K
42
100K
ns
1
tRP
Precharge Time
15
—
15
—
20
—
ns
1
tRRD
Bank to Bank Delay Time
12
—
14
—
14
—
ns
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Min.
Max.
Min.
Max.
Min.
Max.
tRSC
Mode Register Set Cycle Time
12
—
14
—
14
—
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT5SV8M8DT-7K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM
NT5TU32M16DG-3CI 制造商:Nanya Technology Corporation 功能描述:DRAM
NT5TU32M16DG-AC 制造商:Nanya Technology Corporation 功能描述:DRAM
NT5TU32M16DG-ACI 制造商:Nanya Technology Corporation 功能描述:DRAM
NT5TU32M16DG-BE 制造商:Nanya Technology Corporation 功能描述:DRAM
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