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參數(shù)資料
| 型號： | NT5SV8M8DT-7 |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 190K |
| 代理商： | NT5SV8M8DT-7 |
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
15
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents (T
A = 0 to +70 ?C, VDD = 3.3V ?0.3V)
Parameter
Symbol
Test Condition
-6K
-7K
-7
Units
Notes
(6ns)
(7ns)
Operating Current
ICC1
1 bank operation
tRC = tRC(min), t CK = min
Active-Precharge command cycling
without burst operation
60
55
mA
1, 2, 3
Precharge Standby Current
in Power Down Mode
ICC2P
CKE
? V
IL(max), tCK = min,
CS = VIH(min)
1
mA
1
ICC2PS
CKE
? V
IL(max), tCK = Infinity,
CS = VIH(min)
1
mA
1
Precharge Standby Current
in Non-Power Down Mode
ICC2N
CKE
? V
IH(min), tCK = min,
CS = V IH (min)
10
mA
1, 5
ICC2NS
CKE
? V
IH(min), tCK = Infinity,
5
mA
1, 7
No Operating Current
(Active state: 4 bank)
ICC3N
CKE
? V
IH(min), tCK = min,
CS = V IH (min)
30
mA
1, 5
ICC3P
CKE
? V
IL(max), tCK = min,
9
mA
1, 6
Operating Current (Burst
Mode)
ICC4
t CK = min,
Read/ Write command cycling,
Multiple banks active, gapless data,
BL = 4
75
70
mA
1, 3, 4
Auto (CBR) Refresh Current
ICC5
t CK = min, tRC = tRC(min)
CBR command cycling
120
110
mA
1
Self Refresh Current
ICC6
CKE
? 0.2V
1
mA
1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed
on the other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK and t RC .
Input signals are changed up to three times during t
RC (min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t
CK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV8M8DT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5TU32M16DG-3CI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-BE | 制造商:Nanya Technology Corporation 功能描述:DRAM |
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